module ALU (A, B, Control, Result, Zero);

	input		[31:0]	A, B;
	input		[2:0]		Control;
	output	[31:0]	Result;
	output				Zero;
	
	reg	[31:0]	Result;
	
	localparam	Add = 3'b000;
	localparam	Sub = 3'b001;
	localparam	Slt = 3'b010;
	localparam 	Sra = 3'b011;
	localparam	Sll = 3'b100;
	localparam	And = 3'b101;
	localparam	Or  = 3'b110;

	always @(*) begin
		case (Control)
			Add:	Result = A + B;
			Sub:	Result = A - B;
			Slt:	Result = A < B;
			Sra:	Result = A >> B[4:0];
			Sll:	Result = A << B[4:0];
			And:	Result = A & B;
			Or:	Result = A | B;
			default:
					Result = 32'b0;
		endcase
	end
	
	assign Zero = (Result == 0);
endmodule
